The Time Machine is a dedicated hardware module inside of the gCORE processor that dynamically assigns software tasks to cores, allocates resources to tasks, and manages the power state of on-chip resources. Compared to the traditional approach of handling these functions in software, the Time Machine provides superior performance while simplifying the software development process.
L1 Cache
L1 Cache
L1 Cache
Smart
Memory
Controller
Memory
Controller
L1 Cache
L1 Cache
L1 Cache
I/O Interfaces
eg. PCI Express
eg. PCI Express
L1 Cache
L1 Cache
L1 Cache
Smart
Memory
Controller
Memory
Controller
Router
L1 Cache
Time
Machine
Machine
L1 Cache
L1 Cache
The benefits that the Time Machine delivers are:
By eliminating the need for software to manage the relationship between tasks and on-chip resources, the Time Machine greatly simplifies the process of developing real-time multi-thread applications. Furthermore, the Time Machine supports existing multi-task standards such as Linux threads and POSIX so that existing Linux applications can run “as is”.
Processor Cores
SW Thread
SW Thread
Complex, Cumbersome, Slow!!
SW Thread
SW Thread
SW Thread
SW Thread
On-Chip
“Time Machine”
automatically allocates resources across
Grid-on-Chip
automatically allocates resources across
Grid-
Time Machine
Since the Time Machine is responsible for allocating resources on the chip, it has the ability to optimize the power state of on-chip resources depending on what software tasks are running. Since this is done dynamically without software intervention, the gCORE processors are capable of reducing power consumption at the source. Additionally, by putting all of the processor cores to sleep, the Time Machine can achieve a very low standby power, while maintaining the ability to respond to external stimuli.
Factors such as the overhead of managing multiple tasks running on multiple cores, many cores sharing a single system bus, and inefficient memory architectures combine to deteriorate the performance of multi-core processors. The gCORE processors provide the maximum performance available from the cores by removing the cause of such overhead. Task and resource management is handled in the Time Machine, while the Grid on Chip architecture provides maximum bandwidth to all cores.
Number of Core
gCORE Performance
Traditional multi-core performance
